Technical Field
The disclosure relates in general to a method for manufacturing a semiconductor device and the semiconductor device manufactured using the same, and more particularly to a method for manufacturing a semiconductor device using a dummy stop layer, thereby improving the electrical characteristics of the semiconductor device.
Description of the Related Art
Size of semiconductor device has been decreased for these years. Reduction of feature size, improvements of the rate, the efficiency, the density and the cost per integrated circuit unit are the important goals in the semiconductor technology. The electrical properties of the device have to be maintained even improved with the decrease of the size, to meet the requirements of the commercial products in applications. For example, the layers and components with damages, which have considerable effects on the electrical properties, would be one of the important issues of the device for the manufacturers. Generally, a semiconductor device with good electrical performance requires the elements such as the gates and the related layers with excellent properties, such as complete profiles of the components/layers and no unwanted residues remained in the device.
The current nitride planarization process, such as the step of planarizing the contact etch stop layer (CESL) by chemical mechanical polishing (CMP) in the RMG (replacement metal gate) process, generally suffers from over-polishing (or erosion) in an area without or with few poly gate structures. FIG. 1A-FIG. 1B illustrate a conventional method for planarizing the dielectric layers of a semiconductor device and forming the metal gates. After planarizing the dielectric layers such as the oxide layer 13 (i.e. the inter-layered dielectric, ILD) on the CESL 12 and the top portion of the CESL 12 (ex: typically using silicon nitride (SiN) as the material of the CESL on the poly-gate 11) by CMP, the dishing of the oxide layer 13 (i.e. generally referred as the “SiN-CMP problem”) would be occurred in the conventional fabrication of the semiconductor device especially in a large area without or only few poly gate structures, as shown in FIG. 1A. This dishing area AD is a profile defect. After metal deposition and removal (such as by CMP) for replacing the poly gates 11 to form the metal gates 14, the unwanted metal residue 15 would be remained in the dishing area AD, as shown in FIG. 1B.
It is known that the structure a dishing profile (such as dishing of ILD, FIG. 1A) and unwanted metal residue remained in the dishing area (FIG. 1B) generated in the conventional manufacturing method will cause short circuit problem on following metal interconnection process. Accordingly, it is desired to develop a method for forming a complete profile of the elements (such as the gates and dielectric layers) without defects of dishing and residues remained, and the electrical performance of the device still satisfy the product requirements.